Fault tolerance mechanism in chip many-core processors

Accelerating Communication in Single-chip Shared Memory Many-core Processors

Shared Memory stands out as a sine qua non for parallel programming of many commercial multicore processors. For efficiency, shared memory is often implemented with hardware support for cache coherence and memory consistency among the cores. It optimizes patterns of communication that benefit common programming styles. As parallel programming is now mainstream, those common programming styles a...

Self-Adaptive Fault Tolerance in Multi-/Many-Core Systems

Engineering Cross-Layer Fault Tolerance in Many-Core Systems

Engineering modern many-core systems is a challenging task because of their scale and complexity. We cannot focus on ensuring their dependability without understanding its interplay with performance and energy consumption. This calls for developing new structuring mechanisms that step away from the traditional ways systems are developed (such as strict layering, strong encapsulation, abstractio...

Support for Fault Tolerance in Vlsi Processors †

Fault tolerance techniques are used to allow computer systems to continue correct operation despite component failure. Hardware-supported concurrent error-detection and limited fault tolerance in system components, as implemented by coding or replication, are often required. Detection latency can be reduced by increasing the visibility of internal module state using compressed ‘‘signatures’’ of...

Core Power Management Issues in Asymmectric Multi/Many-Core Processors

Power managing is a major issue in designing the future asymmectric multi/many-core processors. The challenge is to provide a solution that has low power consumption, in addition to trade off a small decrease in performance and throughput. Our design includes asymmetric cores in consideration of different points in the view of power-performance efficiency during an application’s execution. In t...